1. Field of the Invention
The invention relates to a technology of oscillator, and more particularly to a relaxation oscillator which reduces the logic delay.
2. Related Art
With the progress of the technology, the electronic technology has been progressed from the earliest vacuum tube and transistor to the integrated circuit chip, which has the quite wide applications. Thus, the electronic products have gradually become the indispensable essentials in the life of the modern human beings. However, the oscillator is an indispensable important element in analog circuit or digital circuit. The relaxation oscillator is an important oscillator in the oscillators. The relaxation oscillator is commonly used in capacitor sensor and single-chip power integrated circuit. Comparing with the LC oscillator, the relaxation oscillator merely requires one kind of energy storage device. The advantages of the relaxation oscillator includes a wide frequency adjustment range, and a high degree of linear control. A well-designed relaxation oscillator should have high stability, wide adjustable frequency range and high linearity.
FIG. 1 illustrates a circuit diagram depicting the relaxation oscillator in the conventional art. Referring to FIG. 1, the relaxation oscillator includes a R-S flip-flop 101 by two NOR gates, a inverter 102, a NOR gate 103, a NOR gate 104, a first P-type MOSFET MP1, a second P-type MOSFET MP2, a third P-type MOSFET MP3, a fourth P-type MOSFET MP4, a first N-type MOSFET MN1, a second N-type MOSFET MN2, a third N-type MOSFET MN3, a fourth N-type MOSFET MN4, a first capacitor 105 and a second capacitor 106. The first N-type MOSFET MN1, the second N-type MOSFET MN2, the third P-type MOSFET MP3 and the fourth P-type MOSFET MP4 are used for bias (current source). In FIG. 1, the labels VBP and VBN are respectively represent the gate voltage bias of the P-type MOSFET and the gate voltage bias of the N-type MOSFET. In order to conveniently describe it, the node labels N1, N2, S3 and S4 are illustrated.
In order to describe the concept of the oscillator, it is assumed that initial logic states of the reset terminal R, the set terminal S, the Q terminal and Q bar terminal of R-S flip-flop 101 are respectively “0”, “1”, “1”, “0”. At this time, the voltage of the node S4 is logic high voltage, the voltage of the node S3 is lower than the threshold voltage of the fourth N-type MOSFET. Because the logic state of the reset terminal R is “0”, and the logic state of the Q terminal is “1”, the voltage of the output terminal of the NOR gate 104 is logic low voltage so that the P-type MOSFET MP2 is turned on. The capacitor 106 is rapidly charged to the logic high voltage such that the voltage of the set terminal S of the R-S flip-flop 101 becomes logic low voltage. Meanwhile, the logic states of the reset terminal R, the set terminal S, Q terminal and the Q′ terminal of the R-S flip-flop 101 are respectively changed to “0”, “0”, “1” “0”.
Afterward, since the logic states of the set terminal S and the Q′ terminal are “0”, the output terminal of the NOR gate 103 outputs logic high voltage such that the P-type MOSFET MP1 is cut off. The capacitor 105 discharges through the N-type MOSFET MN1. When the voltage of the capacitor 105 is discharged to the logic low voltage, the logic states of the reset terminal R, the set terminal S, the Q terminal and the Q′ terminal of the R-S flip-flop 101 are respectively “1”, “0”, “0”, “1”. At this time, since the logic states of the set terminal S and the Q′ terminal of the R-S flip-flop 101 are respectively “0”, “1”, and the logic states of the reset terminal R and the Q terminal of the R-S flip-flop 101 are respectively “1”, “0”, the output terminal of the NOR gate 103 and the output terminal of the NOR gate 104 are logic low voltage, the P-type MOSFETs MP1 and MP2 are turned on. Meanwhile, the capacitor 105 is rapidly charged to logic high voltage, and the logic states of the reset terminal R, the set terminal S, the Q terminal and the Q′ terminal of the R-S flip-flop 101 becomes respectively “0”, “0”, “0”, “1”.
Next, since the logic states of the reset terminal R and the Q terminal of the R-S flip-flop 101 are “0”, the output terminal of the NOR gate 104 outputs a logic high voltage, the P-type MOSFET MP2 is cut off. The capacitor 106 discharges through the N-type MOSFET MN2. When the capacitor 106 is discharged to logic low voltage, the logic states of the reset terminal R, the set terminal S, Q terminal and the Q′ terminal of the R-S flip-flop 101 are respectively changed to “0”, “1”, “1”, “0” again.
FIG. 2 illustrates the waveform depicting the operation of the relaxation oscillator in conventional art. Referring to FIG. 2, people having ordinary skill in the art can see that there is short period during which the voltage of the node N1 and the node N2 are logic low, even though the voltage waveform of the node N1 and the voltage waveform of the node N2 are in antiphase. Thus, the voltage of the node S3 does not be immediately discharge, when the voltage of the node N1 is logic low voltage, and also the voltage of the node S4 does not be immediately discharge, when the voltage of the node N2 is logic low voltage. It causes that the operational frequency of the relaxation oscillator may not be increased, that is to say, the relaxation oscillator consumes more current than other at the same operational frequency.